The present invention relates to a semiconductor device and to a technique for manufacturing the same; and, in particular, the invention relates to a semiconductor device having laterally diffused metal oxide semiconductor field effect transistors (LDMOS•FETs) and to a method of manufacturing the same.
In recent years, LDMOS•FETs (hereinafter referred to merely as LDMOSes) have been used to amplify high-frequency electric power for portable telephone base stations or digital television station transmitters, instead of bipolar transistors, since the LDMOSes produce various advantages, such as simplification of the bias circuits or the provision of high power gain.
An LDMOS is formed in a p-epitaxial layer grown on a p+ substrate, and it is composed of a gate, an n+ source region reaching the bottom of one end of the gate, an n− drain region reaching the bottom of the other end of the gate, an n+ drain region spaced from the latter gate end by the length of the n− drain region, and a p well wherein a channel region is formed.
Although the n+ source region and the n+ drain region of the LDMOS are positioned on the front surface of the chip, a source electrode is formed in the p+ substrate in the rear surface of the chip. Therefore, the n+ source region is connected to the p+ substrate in the rear surface of the chip through a low-resistance p+ source penetrating layer that is diffused in the horizontal direction or a conductor (see, for example, Patent Document 1). The connection of the n+ source region to the p+ substrate through the low-resistance p+ source penetrating layer or the conductor causes a reduction in the inductance or the resistance of the n+ source region so as to prevent the high-frequency power gain of the LDMOS from being lowered.
[Patent Document 1]
Japanese Patent Application Laid-Open No. Hei 5(1993)-218321
In order to obtain a higher gain in the LDMOS, it is necessary that the inductance or the resistance of the n+ source region is made low by at least one of the following methods: (1) the thickness of the p+ substrate is made small; (2) the plane area of the p+ source penetrating layer is enlarged; and (3) the concentration of the p+ source penetrating layer is made high. However, the inventors have found that these methods (1) to (3) have the following problems.